VHDL problem

or

No, (slv =3D x"01") resolves to type boolean as does (sl =3D '1'). I have a function called to_std_logic that takes a boolean and returns a std_logic for just such occasions. So then you have

res

Ok thanks, I thought there would be some kind of conversion function required.

Jon

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KJ's reply hints at a pretty fundamental concept in VHDL: the language- level logic is purposefully different from the digital logic used to describe circuits (true/false vs. hi/lo/x/z/...).

For example, I would imagine KJ's "to_std_logic" function to include a statement like:

output_logic

The trouble I am having is that I have been using Verilog for a number of years but now need to use VHDL. As Verilog lets you do whatever you like, I have been finding VHDL quite hard going. But I am slowly beginning to get the hang of it.

Jon

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