Hello! I've using VHDL for like 2 years or even more but just today i wonde? how it works. Summation function form any package, std_arith for example operates on two arguments. But this one returns std_logic_vector as a result. So i have no ideas how it works when you are using something like this:
signal result : std_logic_vector (15 downto 0); signal arg_1: std_logic_vector (15 downto 0); signal arg_2: std_logic_vector (15 downto 0); signal arg_3: std_logic_vector (15 downto 0);
result