Hi all,
It might be an obvious question but I have a doubt when assigning two buses that are defined with opposite direction.
Here you are an example;
architecture behavioral of buses is signal bus_a: std_logic_vector (0 to 7); signal bus_b: std_logic_vector (7 downto 0); ... begin
-- this doesn't work bus_b
two buses
What do you meant "it doesn't work?". It works fine! In VHDL vectors are assigned left to right, *regardless of how they are declared*. So that code says
bus_b(7) bus_b (i) end loop;
Again, what do you mean "it doesn't work"?
bus_a'range gives you "0 to 7", so the loop results in
bus_b(0) process (bus_a)
I believe your first two examples "work", and the last example doesn't because of the indexing error.
What exactly are you trying to achieve?
kind regards
Alan
Upppsss,
I'm sorry. The second example is wrong,
Thanks Alan for the help.
The thing is that I have been looking for it in a manual that mentions that isn't possible to assign different direction buses in one instruction.
I've tried and it works, so thanks again.
Best regards,
Arkaitz.
Have something to add? Share your thoughts — no account required.
Ask the community — no account required