About ModelSim

Hi, I want to learn using textio. Here I use Read data from scr.txt to IP core RAM and Write them to the text1.txt. I wrote the codes here but it doesn't work. Any suggestions about this is very appreciated. One more thing, when i use Modelsim to Run by step. It alway gives the error information and cannot finish the simulation. I don't what it means.

****************************************************** Trace back: Error opening C:/Documents and Settings/zq500/Local Settings/Temp/xil_1700_6 # while executing # "error $winName" # (procedure "view" line 82) # invoked from within # "view source" # (procedure "vsimcmd::viewProcessSource" line 2) # invoked from within # "vsimcmd::viewProcessSource /check/uut/u0/select_outputb" # ("after" script) # 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local Settings/Temp/xil_1700_6} # 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local Settings/Temp/xil_1700_6} ************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.std_logic_textio.all; use std.textio.all;

entity check is end check;

architecture serial of check is

component checkram port ( addra: IN std_logic_VECTOR(2 downto 0); addrb: IN std_logic_VECTOR(2 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(7 downto 0); wea: IN std_logic); end component;

signal addra: std_logic_vector(2 downto 0):=(others=>'0'); signal addrb: std_logic_vector(2 downto 0):=(others=>'0'); signal dina: std_logic_vector(7 downto 0) :=(others=>'0'); signal doutb: std_logic_vector(7 downto 0) :=(others=>'0'); signal wea: std_logic :='1'; signal wrd: std_logic :='0'; signal clk : std_logic :='0'; signal reset: std_logic :='1'; file from_file:text open READ_MODE is "src.txt"; file to_text:text open WRITE_MODE is " text1.txt"; begin UUT:checkram port map ( addra => addra, addrb => addrb, clka => clk, clkb => clk, dina => dina, doutb => doutb, wea =>wea );

clock_process: PROCESS BEGIN clk '0'); begin if reset='1' then iptaddr :=(others=>'0'); elsif clk'event and clk='1' then while not (endfile(from_file))loop

READLINE(from_file,buf_out); READ(buf_out,num); WRITE (buf_in,doutb); WRITELINE(to_text,buf_in); wea

Reply to
ZHI
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ZHI, Below is what I got. The src.txt was referenced to my current modelsim directory. When I created the file, that error went away. I think the error you got was from the component checkram whose code you did not post.

Newman

--------------------------------------------------------------------- # // # Loading C:\eda\Modeltech_6.2c\win32pe/../std.standard # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_1164(body) # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_arith(body) # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_signed(body) # Loading C:\eda\Modeltech_6.2c\win32pe/../std.textio(body) # Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_textio(body) # Loading work.check(serial) # ** Error: (vsim-7) Failed to open VHDL file "src.txt" in rb mode. # No such file or directory. (errno = ENOENT) # Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/ vhdl_tb/fileio.vhd # ** Warning: (vsim-3473) Component instance "uut : checkram" is not bound. # Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/ vhdl_tb/fileio.vhd

Reply to
Newman

I have a new board where I switched from the xcf08p to the xcf32p serial prom devices. The 32p programs fine and when I cycle power the current jumps up and my test led lights which should mean that the fpga is configured. However, the PPC in the v4fx12 device is dead or not running. Running XMD returns all zeros for the processor ID and I get no output from my bootloader code.

Downloading the fpga manually works fine.

One other difference is that I'm using the revision select lines on the 32p where I didn't on the 08p but the lines are both set correctly and it does appear that the fpga loads but then freezes. Any ideas what might cause this?

Thanks, Clark

Reply to
cpope

Clark, Don't understand the relationship to this thread but I found something on the Xilinx website that may or may not be related to what you are seeing. I did not read the errata.

----------------------------------------------------------------------------------------------- XCF08P, XCF16P, & XCF32P Errata and Deviations from the Data Sheet Intermittent Power Ramp Fa

A test escape has been discovered with the devices named above which for some applications results in device failure during "Power on Reset Activation." Devices that have a VCCint ramp during "Power on Reset Activation" that takes longer than 1ms to reach 1.6V may see failures.

Associated Products: Configuration PROMs

------------------------------------------------------------------------------------------------

Newman

Reply to
Newman

jumps

XMD

32p

does

---------------------

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Thanks, but I get the same result whether I run from Impact or whether I power cycle the board. When I'm using Impact the board power supplies should be well settled so I don't think it's anything to do with transients at power up. -Clark

Reply to
cpope

-------------------------------------------------------------------------------------------------- # invoked from within # "vsimcmd::viewProcessSource /check/uut/u0/ select_outputb"

Reply to
Newman

Turns out I had to change the bitgen option to drive the done pin. Must have been marginal or the pull up strength is different between the xcf08p and xcf32p proms. Mystery solved. -Clark

jumps

32p
Reply to
cpope

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