Hi, I want to learn using textio. Here I use Read data from scr.txt to IP core RAM and Write them to the text1.txt. I wrote the codes here but it doesn't work. Any suggestions about this is very appreciated. One more thing, when i use Modelsim to Run by step. It alway gives the error information and cannot finish the simulation. I don't what it means.
****************************************************** Trace back: Error opening C:/Documents and Settings/zq500/Local Settings/Temp/xil_1700_6 # while executing # "error $winName" # (procedure "view" line 82) # invoked from within # "view source" # (procedure "vsimcmd::viewProcessSource" line 2) # invoked from within # "vsimcmd::viewProcessSource /check/uut/u0/select_outputb" # ("after" script) # 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local Settings/Temp/xil_1700_6} # 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local Settings/Temp/xil_1700_6} ************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.std_logic_textio.all; use std.textio.all;entity check is end check;
architecture serial of check is
component checkram port ( addra: IN std_logic_VECTOR(2 downto 0); addrb: IN std_logic_VECTOR(2 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(7 downto 0); wea: IN std_logic); end component;
signal addra: std_logic_vector(2 downto 0):=(others=>'0'); signal addrb: std_logic_vector(2 downto 0):=(others=>'0'); signal dina: std_logic_vector(7 downto 0) :=(others=>'0'); signal doutb: std_logic_vector(7 downto 0) :=(others=>'0'); signal wea: std_logic :='1'; signal wrd: std_logic :='0'; signal clk : std_logic :='0'; signal reset: std_logic :='1'; file from_file:text open READ_MODE is "src.txt"; file to_text:text open WRITE_MODE is " text1.txt"; begin UUT:checkram port map ( addra => addra, addrb => addrb, clka => clk, clkb => clk, dina => dina, doutb => doutb, wea =>wea );
clock_process: PROCESS BEGIN clk '0'); begin if reset='1' then iptaddr :=(others=>'0'); elsif clk'event and clk='1' then while not (endfile(from_file))loop
READLINE(from_file,buf_out); READ(buf_out,num); WRITE (buf_in,doutb); WRITELINE(to_text,buf_in); wea