post place and route issues for a generic simple n input and gate

Here is what I m trying to implement....in Xilinx 6.2.3 ISE with Modelsim SE. Everything works fine except when I try a post place and route simulation in Modelsim. I get a warning:

# WARNING[1]: generictbw.timesim_vhw(49): No default binding for component: "gen_and_for_loop". (Generic "n" is not on the entity)

and the waveforms dont come up.I looked at the source of the .vhw file that HDL bencher created based on the testbench waveform.Looked pretty ok.

Whats wrong? Any ideas?

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity gen_and_for_loop is generic (n : integer := 2); port(in_and: in std_logic_vector((n-1) downto 0); y:out std_logic); end entity gen_and_for_loop;

architecture behavioral of gen_and_for_loop is begin

and_gate: process (in_and) is variable bit_and: std_logic;

begin bit_and := '1'; for i in 0 to (n-1) loop bit_and := bit_and and in_and(i); end loop;