1. Home
  2. Field-Programmable Gate Arrays
  3. Modelsim: No default binding for component

Modelsim: No default binding for component

Hi, all ,

When simulating the behavioral model, it is ok, but when I simulating the post-translate vhdl model, the simulation can't generate valid results (output are all uncertain state U). from the warning, it seems the UnitUnderTest has not been affiliated, Could you help explain what happens ? thx,

** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for component 'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --> actaully I do have this on the entity.

# ** Warning: (vsim-3473) Component 'uut' is not bound.

best regards, Jimmy

Reply to
Jimmy
Loading thread data ...

If I understand what you are saying, then the problem is that your testbench is setting that generic, but the generic does not exist on the post-translate (I assume post-synthesis?) model.

That would be expected; generics are resolved at synthesis time, and do not appear in the post synthesis models. Take a look at the generated file.

--
My real email is akamail.com@dclark (or something like that).
Reply to
Duane Clark

the

happens ?

component

actaully I

file.

Reply to
Jimmy

I think you don't have your software setting correctly.

Reply to
Wong

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.