To all,
I have been attempting to load a lpm component into a Modelsim project and when I get my test bench compiled and I try to simulate, I get the following error. Note that vosq0_prestore_fifo (my own name) is an instantiated VHDL LPM component from Altera Quartus software using their scfifo function. Below shows the log window. The fatal error is shown below and is detailed because for some reaoson I don't know where to declare a value for the LPM_WIDTHU variable? I had thought that this was already defined? Your help would be appreciated.
Cheers Pino
# Loading work.vosq0_prestore_fifo(rtl) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components # Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl) # Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) # Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl) # Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl) # Loading C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body) # Loading C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a value. # Time: 0 ns Iteration: 0 Instance: /tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component/scfifo14 File: QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/altera_mf.vhd) # FATAL ERROR while loading design