Hi,
I am using a Xilinx Virtex2 Board and would like to have an instruction and data RAM. I was following the guidelines in the XST 7.1 but there still must be something wrong with my description. At the moment around 16000 FF are inferred for my RAM. In addition I get the warning that the rst and ram should be in the sensitive list?
Cheers, Philipp
library ieee; use IEEE.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity ram_prog is generic ( SIZE : integer := 512; WL_ADDR : integer := 8; WL_DATA : integer := 32 ); port ( clk : in std_logic; rst : in std_logic; rw_addr_cp0 : in std_logic_vector(WL_ADDR-1 downto 0); data_in_cp0 : in std_logic_vector(WL_DATA-1 downto 0); data_out_cp0 : out std_logic_vector(WL_DATA-1 downto 0); ew_cp0 : in std_logic ); end ram_prog;
architecture Behavior of ram_prog is
type ram_type is array (0 to SIZE-1) of std_logic_vector (31 downto 0); signal ram : ram_type := ( X"15005304", X"2f501000", X"00000000",.... );
begin PROC_ram : process (clk, rw_addr_cp0) begin if (rst = '0') then -- optional reset data_out_cp0 '0'); elsif (clk'event and clk = '1') then -- memory write: if (ew_cp0 = '1') then if (unsigned(rw_addr_cp0) >= 0 and unsigned(rw_addr_cp0)