Dave,
That is an interesting result, but I was actually more interested in seeing the I/O numbers for the benchmarked designs, instead of adding new (arbitrary?) I/O constraints that may not have been part of the original design. If the I/O constraints were not met, then the results become difficult to interpret.
The only other question in my mind would be whether the different cost tables were used for the Xilinx implementation. However, if both vendors met the I/O constraints, and different cost tables/settings were used for Xilinx (as was done for Altera with DSE) then I agree that the benchmarking is reasonable and there is some validity to them.
SD