can some one give me a hint on how to interface AD9229 a to d converter with stratix II lvds interface? the AD9229 output sample word of 12 bits, however the lvds serdes factor is 10 at the max.
-thanks
- posted
17 years ago
interface ad9229 with altera stratix II
Loading thread data ...
- Vote on answer
- posted
17 years ago
I ran into similar issues with a 1:7 (Channel-Link) receiver design. What I did was to use a 1:4 deserializer on each data channel and capture the 1x clock (in your case the FCO output) with a similar deserializer. Then using the value on the clock (FCO) deserializer I used a simple state machine to frame and compose the 7-bit (12-bit) input data word.
HTH, Gabor