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verilog parser question about `defines

I have a set of verilog files that uses `defines. The same `define is applied to each file to select which code to use.

Is there a way to setup Xilinx ISE so that when processing all verilog files it assumes that a certain `define has been defined ?

Reply to
raphfrk
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vlogcomp has a '-d' option:

evan 63 > vlogcomp Release - ISE Simulator Vlogcomp I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. ... Usage: vlogcomp {options} ... -d Define ; The format of the argument is [=] where is the name of the macro, and is an optional value for the macro

Evan

Reply to
Evan Lavelle

You can also add macros in the GUI under synthesis options (Advanced) "Verilog Macros". Use the same format for definitions. Use a vertical bar to separate multiple entries.

Reply to
Gabor

Thanks

Reply to
raphfrk

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