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Using Verilog to embed the synthesis date and time

Does anyone have a simple way to embed the date and time that a module is compiled into a wire or register in Verilog?

I could use a Perl script to create an `include file with the proper `define statements, but I'm wondering if anyone has a cute way to do this purely in Verilog.

FYI - I'm using Xilinx XST for synthesis.

Thanks!

John P

Reply to
John Providenza
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Reply to
Symon

You can also use cpp for hacks like this.

It's the c pre-processor that processes #include and #ifdef and #define and such.

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Reply to
Hal Murray

Another solution that you may not have considered is to put the timestamp and version information in a header prepended to the download image. This is trivial to do as part of your build process, and avoids the need to have any extra information inside the FPGA itself.

(Obviously this only works if the FPGA is downloaded from a cpu - the cpu will read and strip the version and timestamp info before downloading it into the fpga.)

I (and others) developed something similar when I was at Agilent. We ended up with a lot of information in the headers, including:

- An ID that was unique for each download.

- The name of the person who generated the download file (which came from the username on the computer).

- The part number of the FPGA (extracted from the EDIF file).

- Date stamps for synthesis and PAR (extracted from the EDIF and the PAR report file).

- The version number of the synthesiser and PAR tools (extracted from the respective report files).

All of this was done automatically by the build script, which meant that all fpga download image files had complete traceability back to the exact source files and tool versions. This made bug finding much easier (particularly tool bugs).

Regards, Allan.

Reply to
Allan Herriman

I've embedded the place and route time (year, month, day, hour) in the bitstream in the past as the USERCODE 0xyymmddhh

And embedded the synthesis time in the "HDL" by overriding a top-level generic with a synplify TCL script, which is an idea I saw mentioned somewhere in this NG, or maybe in comp.arch.vhdl.

Cheers, Martin

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Reply to
Martin Thompson

Neat!!

Reply to
Symon

Well, I've ended up using a perl script to modify a line of code in my main include file. I have to remember to run the script, but it's painless other than that.

I decided to use the Unix "epoch" style timestamp in the include file. Trivial C code can decode it and it is a simple 32 bit value to assign to a regr or wire in Verilog.

The C code to print it is like: // 1st, you need to read the value into 'tmp32', then.... printf("Verilog build date was %s", ctime(&tmp32) );

In the include file I have: parameter BLD_EPOCH = 32'd1090435314;

The Perl script that updates the line is: #!/usr/bin/perl -w # # SET_EPOCH.PL # script to update the BLD_EPOCH parameter in the main include file #

# define the include file and a tmp verion of it.... my $file = "../common_v/po_include.v"; my $tmpfile = $file . "2";

my $found = 0;

my $target_string = "^\\s*parameter\\s+BLD_EPOCH\\s+=\\s+32'd";

my $epoch = time();

# open the original file for reading... open(ORIG, "

Reply to
John Providenza

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