Xilinx ISE 6.3i 'include construct issue


A Verilog project I'm working on uses 'include statement in some of its modules (.v files) to reference some pre-defined variables in this manner: 'include "file.vh".

The file, "file.vh" is in the same path as the veil modules that use that statement. ISE complains that it "Could not find include file 'file.vh' in spite of copying file.vh to the project directory and adding it to the project source files so that it appears in the "Sources in Project" tab that displays the source hierarchy.

What can I do to fix this error w/out having to add all the defined variables to each Verilog module.



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Nju Njoroge
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