Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)

I tried it with ncverilog, and didn't get the bad answer. Is it posssible that the ; at the end of `define is causing the problem?

Try this in your module:

initial $display ("NUM_COUNTER_BITS = %d", `NUM_COUNTER_BITS);

Thanks for the suggestion. I tried this below: $display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);

and it does print out "NUM_COUNTER_CYCLES=256" in ModelSim. However, in the actual waveform, the value is still 5 and the logic uses that incorrect value.

The main reason I want to use `define directive is because I'm using a `include file since this constant is used in many other modules.

NN

By the way, the ";" at the end of the `define directive was a typo in my original posting. I don't have it in the real code.

NN

One difference is that parameters can be over-ridden by the calling module via the defparam command. Not true with `define.

$display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);

isn't the same as:

$display("NUM_COUNTER_CYCLES=%d", NUM_COUNTER_CYCLES);

so maybe there's something else going on in your code?

Yeah, I've fought (and lost) that battle.

Another thing you could do is simply put the parameters on your tool's command line. The two arguments against this are:

a) Some tools (like Xilinx XST) don't support setting parameters on the command line, and b) It's convenient to have the definitions for the particular build available as a source file, rather than buried in a script somewhere.

The ideal is to be able to build different versions of your chip from source without modifying the source. Sometimes practical issues get in the way.

-a

Some tools let you override `defines from the command line.

-a