>>> Jim Granville wrote: >>>> Imagine a stacked die FPGA, with a large VFast SRAM, and Config device ? >>>
>>> Uwe Bonnes wrote: >>> You're dreaming >>
>>
>> Of course, but it is realistic of what might be on our desks in 2-3 yrs time ? [Which means we should be thinking about it now, and if one >> FPGA vendor sees this, and the others miss it == big lead] >>
>> Other > We are not just inward-looking. Of course we also look at the > possibilities of stacked die. > But the applications flexibility that makes FPGAs so great, works > against die stacking. > Pentiums and cell phones are more "single purpose" where the > manufacturer can aim at a well-defined application without too many > variations. FPGAs are used all over the place, in all sorts of > constellations. Which one should we concentate on, which one to ignore? > Just my opinion... > Peter Alfke
Further on this Stacked die discussion, I see the first example of "stacking technology" in a roadmap for the merchant Microcontroller market, which is about as far from "single purpose" as you can get.
See pages 6-9 of :
formatting link
[You can also see a smallish CPLD in some of these feature-packed devices...Ethernet.CAN.USB.2MF.96KR]
Since ST have strong Burst FLASH, and Microcontoller/ASIC product lines, this is easy for them to do.
So I believe it is more a question of who will be first to do this, in the FFGA sector ? [Altera/Lattice/Xilinx...] ?
-jg