Hi all again,
I have a fairly straight forward systolic array design which uses the fixed_point type. It simulates fine for the behavioral simulation. It synthesizes fine (there are a few warnings, but they appear to be OK)... but when I try to do a post-synthesis simulation in ModelSim, I get:
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): Prefix of a slice must be a 1 dimensional array. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): Prefix of a slice must be a 1 dimensional array. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): Unknown identifier 'std_logic_vector2'. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): Prefix of a slice must be a 1 dimensional array. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): Prefix of a slice must be a 1 dimensional array. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): Unknown identifier 'std_logic_vector2'. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Prefix of a slice must be a 1 dimensional array. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Prefix of a slice must be a 1 dimensional array. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Prefix of a slice must be a 1 dimensional array. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Unknown identifier 'std_logic_vector3'. ** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(241): VHDL Compiler exitingDo I need to include some library that I'm not? What might be the issue?
Thanks in advance,
Sergey