post-synthesis simulation issues with ModelSim

Nov 05, 2006 3 Replies
S

Hi all again,



I have a fairly straight forward systolic array design which uses the fixed_point type. It simulates fine for the behavioral simulation. It synthesizes fine (there are a few warnings, but they appear to be OK)... but when I try to do a post-synthesis simulation in ModelSim, I get:


** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): Prefix of a slice must be a 1 dimensional array.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): Prefix of a slice must be a 1 dimensional array.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): Unknown identifier 'std_logic_vector2'.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): Prefix of a slice must be a 1 dimensional array.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): Prefix of a slice must be a 1 dimensional array.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): Unknown identifier 'std_logic_vector2'.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Prefix of a slice must be a 1 dimensional array.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Prefix of a slice must be a 1 dimensional array.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Prefix of a slice must be a 1 dimensional array.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): Unknown identifier 'std_logic_vector3'.
** Error: C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(241): VHDL Compiler exiting

Do I need to include some library that I'm not? What might be the issue?



Thanks in advance,



Sergey



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S

Forgot to include the actual lines that its erroring on:

inmatA : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 ); inmatB : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 ); outmat : out STD_LOGIC_VECTOR3 ( 3 downto 0 , 3 downto 0 , 16 downto 0 )

(I see that they're declared as multi-dimensional and probably aren't supposed to be... but why is Xilinx translating them that way, and what can I do about it?)

-- Sergey

sergey wrote:

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K

add this to your code

library VITAL; use VITAL.VITAL_TIMING.ALL;

regards, Krishna Janumanchi

sergey wrote:

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S

Dear Krishna,

Thank you for your response.

Which file do I add that to? The post-synthesis VHDL file, or the pre-synthesis top-level module?

Also, I tried adding it to the post-synthesis file and ModelSim can't find library VITAL. Is that something only available with the full version? (I'm using the starter version).

Thanks again,

Sergey

snipped-for-privacy@gmail.com wrote:

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):

C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(241):

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