ISE 8.1: simulation modelsm & tbw generated in Verilog instead of VHDL?!


Can't find in help / documentation: where in ISE 8.1 are the options that decide what language will be used for generation of simulation models and into what language the testebnch (tbw) file will be translated?

In ISE 7.1 there was a neat option "Generated Simulation Language" in project top properties. It's gone in 8.1. Is it necessary to set each process "Generate Post-Synthesis/Post-Translate/etc. Simulation Model" individually? Default value in my installation is Verilog, can it be changed to VHDL?

And I have no idea how to change test bencher so that for *.tbw file it generates VHDL (*.vhf) instead of Verilog (*.vf).

Any help appreciated!


Reply to
Loading thread data ...

Double click the project name in "Sources for" tree at top left in ISE 8.1. That opens up a properties page that appeared when you created a new project. You can change the simulator and its language from there.

Reply to
Uday Godbole

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.