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Went from Xilinx to Altera: Cyclone-II and I/O pullup?

I'm a longtime Xilinx user, and I've recently switched over to the dark side :)

Anyway, I'm new to Quartus-II Web Edition, and I'm trying to port a project from my Xess XSA-3S1000 board to a Altera Cyclone-II Starter Kit. I've run into a problem where I have bidi I/Os which need a PULLUP. The Xilinx Spartan-3's I/Os supported a PULLUP constraint, specified in Xilinx's *.UCF file. I searched Altera's website, but I can't find how to specify a pullup on the Cyclone-II's I/Os? Can someone give me a quick pointer?

...

Also, is there a way to directly import a $readmemh file into Quartus-II ROM-initialization file (*.mif) ? So far, I've been running a Verilog-program to convert the $readmemh files into *.mif files. It works, but it's an extra-step I'd like to eliminate.

...

So far, I like Quartus-II's speed. Synthesizing my design is almost

2X fast in Quartus II 7.1, as it was in Xilinx Webpack 9.1i.03.

On top of that, Quartus-II's Verilog-parser is uniformly better across the board. (Well, except for the `macro preprocessor having problems with multiple macro-arguments that span 2 or more textlines.)

Xilinx's XST synthesis gets tripped up by obvious Verilog-2001 constructs, like:

reg [7:0] memory [0:255]; always @* mux_out = memory[ addr ];

And Xilinx's XST doesn't like nested procedural for-loops: always @* integer i,j; for ( i = 0; i < MAX_I; i = i + 1 ) for ( j = i; j < MAX_I; j = j + 1 ) //

Reply to
Xilinx user
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Welcome to the dark side !

Use "Weak Pull-Up Resistor" in the Assignment Editor.

The Fitter - Resource - Output Pins section of the Compilation report should tell you if your assignment was succesfull.

Grt, Karl.

Reply to
Karl

Xilinx user,

Welcome to the sunny side. If you sense this is the dark one, you have been severely brainwashed in the past.

My friend and colleague Karl has covered your question regarding I/O pullups pretty well, so no need to expand on this.

As to initializing ROMs in Verilog, the Quartus documentation, Volume 1, page 326 (in my beta docs) give the following simple template:

module ram_with_init( output reg [7:0] q, input [7:0] d, input [4:0] write_address, read_address, input we, clk ); reg [7:0] mem [0:31]; integer i; initial begin for (i = 0; i < 32; i = i + 1) mem[i] = i[7:0]; end always @ (posedge clk) begin if (we) mem[write_address]

Reply to
Ben Twijnstra

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