Xilinx, How to generate PAD file, from the UCF file

Jan 03, 2008 3 Replies
G

Hi,



I am working on a Xilinx Virtex5 design. I generated a pin lock file (ucf) and have a top level verilog file. Top level verilog file does not have any code, but it has only IO declarations.And I want to generate the pad file out of this.



The issue is that since it is an empty design, I get the following error message, " NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper. "



I tried -u options in MAP, and I have also enable add IO buffer options in XST, but it still gives the same error.



I know I can write some dummy logic and generate the pad file, but was wondering if there is any easier method of doing this?



Does anyone know how can I give this SAVE attribute as mentioned in the error above? Or is there any way to generate the pad file.



Regards, Goli


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J

What info do you want to save to this PAD file? You can give ADEPT

formatting link
a try to see if it may do what you want. If it doesn't, please let me know and I will see if I can help.

Cheers, Jim

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K

Your outputs might be getting stripped out in synthesis. You could rectify this by just tying by using "syn_keep" constraints or just by tying them high or low. Like this:

module top (input clk, reset, output a, b, c); assign a=0; assign b=0; assign c=0; endmodule

That should keep the outputs from getting removed.

-Kevin

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G

Hi Jim,

Thanks a lot for the link. I really found this tool very useful.

Kevin,

thanks for the reply. I know I can do that but I was looking for a simpler alternative.

-- Goli

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