XST synthesis

Was wondering if anyone would be kind enough to help me out here - I've been struggling with a synthesis problem in Webpack, and would appreciate being pointed in the right direction :-)

XST is telling me:

WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Sources are: data5:data, data4:data, data3:data, data2:data, data1:data, data:data WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Sources are: I181_0:O, I180_0:O WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Sources are: c:data, rc:dataOut, mul:data, timer1:data

... I'm not sure what the syntax data5:data means, but there are 6 of them, and the only direct manipulation of 'data' (it's a module port) is:

assign data = `ADDSUB ? addsub : `MSB'bz; assign data = `MULTIPLY ? multiply : `MSB'bz; assign data = `DIVIDE ? divide : `MSB'bz; assign data = `LOGIC ? logic : `MSB'bz; assign data = `SHIFT ? shift : `MSB'bz; assign data = `JAL ? pc : `MSB'bz;

... which (coincidentally?) has 6 assign statements... The definitions of the `PARAMETERS are as follows:

`define ADDSUB (opMajor == 4'b0001) `define MULTIPLY (opMajor == 4'b0100 & opMinor[1] == 1'b1) `define DIVIDE (opMajor == 4'b0100 & opMinor[1] == 1'b0) `define LOGIC (opMajor == 4'b0011) `define SHIFT (opMajor == 4'b0111) `define JAL ((opMajor == 4'b0000) & (opMinor == 4'b0000))

... which seem orthogonal. Is the synthesis tool complaining because there are conflicts between the modules, then ? Icarus verilog seemed to handle it all in its' stride while simulating (though I know that's no guarantee :-) I was under the impression that a port declared inout could be assigned multiple times, if it only has one driver at a time, and if all others drive it to Z. Presumably I'm not managing to keep it to one driver across all the modules, then ?

Cheers, Simon

been

being

Thanks for the help:-)

I was going to write this ...

----8

Use a case statement inside of an always block or a function.

Replace this portion with

assign data = `ADDSUB ? addsub : `MULTIPLY ? multiply : `DIVIDE ? divide : `LOGIC ? logic : `SHIFT ? shift : `JAL ? pc : `MSB'bz;

and it will work.

You can't use multiple assigns on same wire variable.

Kelvin

When each of the ?: values was all Z, this idiom used to correctly infer a set of TBUFs. Now that there are 0.25 TBUF/LUT and plenty of F5, etc. MUXes, this implementation style is inferior to implementing a MUX tree in LUTs.

Jan Gray, Gray Research LLC

i thought multiple assign to same wire is a syntaz violation. put it in an always block, and replace assign, it's correct also.

Kelvin