I'm doing my work using next tutorial: "MultiPoint Synthesis Using Synplify Pro for Xilinx". I defined three compile points in the top-level .sdc file: Block_1 Block_2 Block_3 After that I run synthesis. And I have next error: @E: FA165 :"../../top/top_level.v" - Unable to insert correct pad for port TDO. It is driven by a tristate in an unreachable hierarchy (Blackbox or Compile Point). This output port TDO located in Block_2 module. Without compile points it works correctly.
Verilog code for top_level.v module top_level( .. .. .. TDO ); .. .. .. output TDO; .. .. Block_2 uBlock_2( .. .TDO (TDO), .. );
.. endmodule
May be I have to define this port in constraint file ?