In ISE 8.1i creating a Testbench waveform does not work for a Schematic TOP Level project with VHDL set as the language for HDL Functional Language Model (Verilog is the default, in 8.1i the Simulation generated language option was removed from the project properties)
Testbench waveform works for Verilog netlist and it works in 7.1i for VHDL too. I tried 8.1i SP1 but it did not help.
Does anyone have the same problem?
Thanks