Hello All, I'm trying to get Linux working on the Xilinx ML310 using a PCI hardware configuration, other than the one provided by Xilinx. I have a base configuration which I created using the EDK 7.1sp1.
I've been able to compile a 2.4.30pre-1 linuxppc kernel, after making little modifications to the source due to some values (like the device ID of the OPB-PCI bridge) were hardcoded into it. Right now I have the kernel more or less working (there are sporadic kernel panics) if I use no PCI devices but the IDE controller. In order to get the IDE working I had to use as interrupt the 31. In the hardware configuration this interrupt is connected to the PCI-SBR pin (by the way, what is this pin for?).
If I include other PCI device into the kernel configuration, the driver is able to read the registers and memory from the device. The problem is related to the interrupts, it seems that only the "SBR interrupt" is being received. At this point, I have some questions about how interrupts are delivered from the PCI devices to the interrupt controller.
Looking at the system.vhd I see that the SBR pin is connected to the interrupt 0, lines PCI_INT are connected to interrupts 1 to 6, and the IP2INTC line is connected to interrupt 12. The problem is that I don't know which line is actually used to deliver the interrupts coming from the PCI devices. I've tried using all of them, but all attempts were failed.
On the PCI base configuration provided by Xilinx I see that they use a IPcore called misc_logic, which seems to merge all interrupts lines (some of them are even inverted) into a single one, but I do not understand why should I do it. Could anybody explain me the actual reason?
It would be great if somebody could explain me how does the whole thing related to the interrupts from PCI devices works. At least I would like to know which interrupt line is supposed to be asserted when the ethernet card, the USB bridge (or whatever PCI device you prefer) launches an interrupt, so then I can try looking into the linux kernel code to fix the problem knowing that the interrupt line is being asserted.
Thanks in advance and best regards, Isaac