Hi,
I'm pretty new to verilog and I am trying to write code to compute a mean and store it in RAM. I update the ram each time a new sample comes in and thus the ram becomes my second addend. Here is a bit of the code. Why am I getting multi-source in unit on cal_ram_di?
always @(posedge clk) begin if(~done & stepCnt == 0) begin if(cal_cnt == 0) begin addend1
Are you sure this is all the code which assigns to cal_ram_di? What you show is a single always block so it's difficult to get a multi-source out of it. Check where else you're using cal_ram_di to see if you're declaring it as input or whether you're assigning to it again.
Another comment is that you can change the "if (cal_cnt==0) to a case statement which might give you better performance.
Probably. The synthesis tool probably found an occassion where two or more if-conditions are possible met at the same time, hence the signal is assigned in two different places, and the tool doesn't know which of the assigments is to be carried out.
As a general rule: Each signal should only be assigned in one single always-block, or process-construct in VHDL, not in several, or you almost always run into the kind of problem you're having now.
You need to have ONE block of instructions that covers the assignment of "cal_ram_di" for all possible cases, and "cal_ram_di" should only be read in other always-blocks, never be assigned.
Maybe a little insight into synthesis tools might help here. What a synthesis tool does (after checking the syntax and so on) is search your code for certain templates. These templates you can find in the ISE-documentation. For example, if the tool finds something like
counter
If only synthesis tools were that smart. Independent of the condition the register is assigned, you will get this error if two always blocks assign a register. Just don't do it. One solution is to move all the assignment into a combinational always block ie one which generates the D input of the flops to be assigned. Then you can add multiple independent if conditions more easily and assign the d input to the register in a clocked always block.
ie always @(*) begin if (some condition) cal_ram_di_d = first; if (some other condition) cal_ram_di_d = second; end
always @(posedge clk) cal_ram_di
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