If you use a continuous or non-blocking assignment in Verilog and the right hand expression is something that in a real device takes time to become valid after the inputs become valid, how do you ensure the output IS valid when you want to use it?
For example:
input [1000:0] megaparity; assign foo = ^megaparity;
always @(posedge clk) // megaparity valid on this clk saved_parity