If you use a continuous or non-blocking assignment in Verilog and the right hand expression is something that in a real device takes time to become valid after the inputs become valid, how do you ensure the output IS valid when you want to use it?
For example:
input [1000:0] megaparity; assign foo = ^megaparity;
always @(posedge clk) // megaparity valid on this clk saved_parity
Then static timing will fail.
You might synchronize foo to the system clock, and enable the assignment only when foo is valid.
-- Mike Treseler
This is called a multi-cycle timing. You need to figure out just how slow it will be and use a clock enable on your register. My Verilog is rusty, but I am pretty sure you just use an IF statement, something like this example I pulled from some public code.
always @(posedge clk) begin : sr_proc if (rst == 1'b 1) begin shift_reg
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