Xilinx (without init value) has a constant value of 0?

I am constantly getting the following warnings when compiling in Xilinx: FF/Latch (without init value) has a constant value of 0 in block

I do not understand why this happens since I set thresh to 0 on rst signal. Here's my code:

//determine the threshold value reg[7:0] thresh; always @(posedge clk) begin if(~done & stepCnt==2 & cal_cnt==3 & sampCtr==511) thresh

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Yes ALPHA is always even. Thanks. However, Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block has also come up as a warning which I do not understand. And finally, FFs/Latches (without init value) have a constant value of 0 in block also comes up which corresponds to the following code: always @(posedge PCI_CLK) begin if(~PCI_RSTn) begin PCI_DMAaddr

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Again I don't think that "without init value" is the point of the message. I imagine if you had defined PCI_DMAoutaddr something like:

reg [31:0] PCI_DMAoutaddr = 32'b0;

you wouldn't see that part of the message, but it wouldn't change the fact that it never takes a value other than zero. This can be traced back to DMAwordsWritten also staying zero, unless you have left out some code in the first always block?

I've looked at some of my synthesis reports and found the same parenthetical "without init value" on signals that had asynchronous reset terms, so I'm concluding that Xilinx's idea of "init value" is a specified INIT constraint as applied to a flip-flop, which can be different from the asynchronous or synchronous reset term. This is true for FPGA's because the flip-flops take there initial value from the bitstream, which does not have to be the same value as the flip-flop reset term. In any case I'm sure they write this in parentheses because it is not the important part of the warning. It is relevant, because if you had specified an init value other than zero, it could not remove the flip-flop from the design because the value would no longer be constant.

HTH, Gabor

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