Hi I am writing synthesizable Verilog code for a DPRAM. It has two ports, Port A and Port B. For each port theres is a separate clock and separate clock_enable. This is the code I wrote
reg [ 4: 0] read_addr_a; reg [ 4: 0] read_addr_b;
always @ (posedge clock0) if (clocken0) begin read_addr_a