Hi I am writing synthesizable Verilog code for a DPRAM. It has two ports, Port A and Port B. For each port theres is a separate clock and separate clock_enable. This is the code I wrote
reg [ 4: 0] read_addr_a; reg [ 4: 0] read_addr_b;
always @ (posedge clock0) if (clocken0) begin read_addr_a
What you have is two FF driving the same wire, which is not allowed and not synthesizable. That has nothing to do with the clock. Eventhough you have the same clock, it is still not synthesizable.
Hendra
You have to do all the operation in a signal process ...
like (VHDL sorry ...)
process (clka, clkb) begin if rising_edge(clka) then if clken_a = '1' then ... end if; end if; if rising_edge(clkb) then if clken_b = '1' then ... end if; end if; end if;
The problem is that you're trying to write to both address registers using both clocks. Think about the hardware and you'll realize that this is not necessary. read_addr_a should be written by clock0 by clken0 only and the similarly for read_addr_b, ie
always @ (posedge clock0) if (clocken0) begin read_addr_a
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