The following code is my first Verilog program. It's running at 25MHz and that's what the counter is for. I'm trying to accomplish the same thing by shifting bits instead of hard coding the output in case statements. I tried LED>1 to no avail. Any comments and suggestions are appreciated!
Thanks! Kate
module ledbounce(clk, LED); input clk; output [3:0] LED;
reg [19:0] cnt1; reg [2:0] cnt2; reg a, b, c, d; wire cnt1max = (cnt1==1000000);
always @(posedge clk) if(cnt1max) cnt1
by
tried
[snip code]First, it's worth noting that you are more likely to get an answer on comp.lang.verilog than here - although many of us read both groups.
Second, you can't manipulate output LED as you tried, because it's a wire, not a reg - you declared it correctly as an output, but outputs are wires by default. You need to do the shift operations on the register you've represented as a,b,c,d.
Third, although I can see the sense in your counter arrangement, the second counter is not really necessary - you could use the "bouncing bit" 4-bit register as its own counter.
Fourth, you REALLY need to think about reset strategy - in many FPGA and CPLD devices, flip-flops start life with zero in them, but it's a bad idea to rely on this.
So, here's my suggestion:
(1) Throw away your cnt2 logic and registers a,b,c,d. (2) Make the bouncing-bit counter like this:
reg LeftNotRight; reg [3:0] LED; // This in addition to the output declaration ... always @(posedge clk or posedge reset) if (reset) begin LED
I don't see why what she's done wouldn't work. Her registers a,b,c, and d change at the clock edge and the LED wires are connected to the outputs of the registers.
The only problem I might see is that it runs a bit fast. The "state machine" changes states at 25Hz and it might be hard to see the LEDs blink that quickly.
-Kevin
The code as presented was fine, yes. I was talking about the attempt to set LED > 1, as mentioned at the start of the original post. Sorry I didn't make that clear.
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Jonathan Bromley, Consultant
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BEAUTIFUL!!! Thanks Jonathan! This is exactly what I was looking for! I appreciate your response! I'll move my further discussions to comp.lang.verilog.
Thanks again! Kate
and
UK
snipped-for-privacy@doulos.com
Thanks much Jonathan!!! Worked like a charm!!! I'll move all further discussions to comp.lang.verilog
Thanks again!
and
UK
snipped-for-privacy@doulos.com
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