Dear group,
I have a work around for this issue but it seems a little strange that the Q1 from the Master ISERDES is acting a little flaky. It appears that it copies Q2 from time to time. The rest of the bits seem fine.
Perhaps this is how I assigned the same signal to both CLK and OCLK and perhaps one should be delayed from the other?
Or perhaps this is an artifact of using 7x frequency and I am the only one on this planet who is using 7x?
Or perhaps its an artifact of using the all the output bits, including Q5 and Q6 from the slave, and not just the 7 suggested by Xilinx ?
Brad Smallridge Ai Vision
cam2_x0_ibufd_inst : IBUFDS port map ( O => cam2_x0, I => cam2_in(1), IB => cam2_in(0) );
x0_iserdes_master : ISERDES generic map ( BITSLIP_ENABLE => FALSE, -- TRUE FALSE DATA_RATE => "SDR", -- DDR SDR DATA_WIDTH => 6, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8 INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING" IOBDELAY => "IFD", -- delay chain "NONE","IBUF","IFD","BOTH" IOBDELAY_TYPE => "VARIABLE",-- tap delay "DEFAULT", "FIXED","VARIABLE" IOBDELAY_VALUE => 15, -- initial tap delay 0 to 63 NUM_CE => 1, -- clock enables 1,2 SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, Q1 => cam2_x0_bit(0), Q2 => cam2_x0_bit(1), Q3 => cam2_x0_bit(2), Q4 => cam2_x0_bit(3), Q5 => cam2_x0_bit(4), Q6 => cam2_x0_bit(5), SHIFTOUT1 => cam2_x0_shift1, SHIFTOUT2 => cam2_x0_shift2, BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => cam2_clk7x, CLKDIV => cam2_xclk, D => cam2_x0, DLYCE => cam2_dlyce, DLYINC => cam2_dlyinc, DLYRST => cam2_dlyrst, OCLK => cam2_clk7x, REV => '0', SHIFTIN1 => '0', SHIFTIN2 => '0', SR => cam2_reset );
x0_iserdes_slave : ISERDES generic map ( BITSLIP_ENABLE => FALSE, -- TRUE FALSE DATA_RATE => "SDR", -- "DDR" "SDR" DATA_WIDTH => 6, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8 INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING" IOBDELAY => "IFD", -- delay chain "NONE","IBUF","IFD","BOTH" IOBDELAY_TYPE => "VARIABLE",-- tap delay "DEFAULT", "FIXED","VARIABLE" IOBDELAY_VALUE => 15, -- initial tap delay 0 to 63 NUM_CE => 1, -- clock enables 1,2 SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE" SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, Q1 => open, Q2 => open, Q3 => cam2_x0_bit(6), Q4 => cam2_x0_bit(7), Q5 => cam2_x0_bit(8), Q6 => cam2_x0_bit(9), SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => cam2_clk7x, CLKDIV => cam2_xclk, D => '0', DLYCE => cam2_dlyce, DLYINC => cam2_dlyinc, DLYRST => cam2_dlyrst, OCLK => cam2_clk7x, REV => '0', SHIFTIN1 => cam2_x0_shift1, SHIFTIN2 => cam2_x0_shift2, SR => cam2_reset );