4VSX35 LOC placements?

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How does one find the legal values where "things" can be placed? Is it
or is the Xilinx documentation distinctly lacking in explicit detail?

I have a design in which ldvs is used to output 32 data pairs, 2 clock
pairs and
2 other pairs  from a clock input pair at 512MHz. The input clock
passes thru an
IBUFDS, a BUFIO, a BUFR dividing by 4 to a BUFG which drives things in
fabric.  The 512MHz and 128MHz from the BUFIO and BUFR drive OSERDES
and a pair of ODDR for the clock outputs.

There are no problems at the place and route stage if nothing is
but then the pin placements are not good for pcb layout. It bombs if I
try to use
a constraint in the ucf file to place even the clock input in bank 10
in an initial
attempt to persuade it to place the lvds outputs in banks  6, 8 and 10.

Bank 10 is "adjacent" to banks 6 and 8, right?

The error message is that "clk128 cannot possibly be routed to
bufg_inst (placed in clock region 6) since it is too far away from
source  BUFR
(placed in clock region 7)". I would like to LOC the BUFR and even the
but where? The relationship between banks and regions and the general
of detail is confusing me. Maybe I need to take a break. IDELAYCTRL
will also
need to be placed but where? I know there are 16 of them!


Re: 4VSX35 LOC placements?
ADEPT will answer most (if not all) of your questions. Check it out at

http://home.comcast.net/~jimwu88/tools/adept /


snipped-for-privacy@jb.man.ac.uk wrote:
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Re: 4VSX35 LOC placements?
Hi Jim,

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I would love to use it but I am running ISE 8.1.03i on
linux ( fedora core 4). If I can't get an answer, I will
install on Windows and try it.

Are Xilinx hiding the information so you can give
away the tool with the answers for free? How did
you get the knowledge?


Re: 4VSX35 LOC placements?
All information is available either in device user guide or from the
ISE tools (PACE, FPGA_EDITOR, etc). ADEPT presents these information in
an easier-to-read way (or so I hope)  ;)


snipped-for-privacy@jb.man.ac.uk wrote:
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