Hi all,
I work with ISE.6.3.3i and ModelSim 5.8c the target is a Virtex II Pro 70 -6.
My design has been P&R for two frequencies : 50 MHz and 80MHz.
In this two cases, the timing report indicates no errors and all the timing constraints were achieved. The timing constraints are essentially a PERIOD constraint and several FROM TO (all pads all FF, all pads all RAM, all FF all RAM).
But at timing simulation, some differences appear.
At the lower frequency, the design responds well to the stimuli and they were no warnings.
At 80 MHz, after my reset phasis, I see two kinds of warnings :
- X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK 2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK
appearing at each period of the simulation and the outputs of my design aren't defined (all reds)..
My problem is that the timing report detects no errors so I don't know where to search.
Does somebody has an advice to resolve these warnings or pointers to have more informations about SETUP TIMING or HOLD TIMING ???
thank you very much for your help.
Michel