how to get XST to infer 8:1 mux or just hard code it?

Usually your best chance of getting it is with a CASE statement. No guarantees though as synthesisers are notoriously unpredictable.

You can also try structuring your VHDL to suggest a element layout.

Instantiating macros in your HDL will give you a more exact structure.

-- John Adair Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.

look in the XST templates.

In Verilog

x

I'm not certain about XST but my favorite trick with Synplify is to define my selection as an 8-bit wire and select one of the bits. Simple! XST ? (Verilog) wire [2:0] Sel; wire [7:0] MuxItems = {In1, InA, InB, Out1, Mid7, Result, whatA, whatB}; wire MuxOut = MuxItems[Sel];

I don't understand how you would make a 4:1 mux in a Xilinx without making it out of smaller muxes. The LUTs only have 4 inputs, so you can't make a

4:1 mux out of a single LUT. You need two LUTs plus another F5 mux.

-Kevin

Well, there are a few ways I can think of:

1) Use TBUFs to wire-OR LUT outputs together 2) Use the OR cascade in virtexII in the same way, preferable because it is faster and more plentiful 3) If you can accept a 16 clock set-up time, you can use the SRL16 as a programmable LUT. The programmer uses 2.5 slices, and loads up the SRL16 (or a word wide bank of them) with the appropriate pattern to connect the selected input to the output ( patterns are for a mux with enable are X"0000",X"AAAA",X"CCCC",X"F0F0",X"FF00"). This is useful for minimum propagation time 4:1 muxes for applications where the selection is relatively static, or is otherwise allowed time to complete. Yes, I have used it. 4) if your sources to the mux have available terms or come from flip-flops, you can substitute a 4 input OR for each MUX bit by having your select logic gate off all but one of the inputs at any given time. If the inputs are from flip-flops, you can use the sync reset on the flip-flops for the gate function without having to add logic in front of the flip-flop other than the decoder on the reset.

Kev> > I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

I have not tried coding this in XST, but I am pretty sure it does not result in an 8:1 mux. The syntax you show is a priority selector. That means that it indicates an order of precedence. Even though it makes no difference since the selectors in each case are mutually exclusive, it is unlikely that this will be optimized to a proper mux.

The recommended coding style would be a case statement, which by definition has mutually exclusive selections of a single control variable.

A better coding method for bus muxes would be to pre-decode the selectors so that each of the 8 mux inputs has a separate enable. Then an 8 input mux can be done in just two levels of LUTs. The first level can encode the AND gates and one OR gate for combining two inputs. The second level is an four input OR gate for the final output.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

When trying to create a mux with a case statement XST requires the output be a reg. Why is this and would making it a reg(latch) make the mux slower?

Matt

using

necessarily

using

or

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

use case statement to infer 4:1 mux case sel is  when "00"=>   -- or use basic gates to form 2:1 mux then use this mux in structural way this will help synthesizer to optimise logic at boolean optimisation level

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

When trying to create a mux with a case statement VERILOG requires the use of reg elements. These do not have to end up as registers and will not slow the design. Assemble the case statement inside an always block with all the inputs in the sensitivity list. The resulting "reg" values assigned in the case statement are effectively wires.

- John_H

Declar "Assignments to a reg are made by procedural assignments (see 6.2 and

9.2). Since the reg holds a value between assignments, it can be used to model hardware registers. Edge-sensitive (i.e., flip-flops) and level sensitive (i.e., RS and transparent latches) storage elements can be modeled. A reg needs not represent a hardware storage element since it can also be used to represent combinatorial logic."

Instead of "reg," think "sticky." (But type "reg"!)

Bob Perlman Cambrian Design Works

necessarily

using

or

Ray, OK, I'll grant that in special cases there are other possible structures. #2 sounds a little weird, like self-modifying code. Don't forget #5: one can set the contents of a blockRAM so that the address lines can be used for mux control and data.

-Kevin

is

(or a

selected

relatively

flip-flops, you

gate

function

decoder on

using

or

making

a

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

rickman wrote

I did miss 1 detail, I use the form in both cont = assignments and the always The recommended coding style would be a case statement, which by

Thanks for reminding me of And/Or, there may be occasions where I just might need that trick. So far I have used MUXF5,6s for some sneek paths, then rewrote the whole module to do better job without.

regards

johnjakson_usa_com

Ray, I'm sure it's a valuable design technique. I think it just reminded me of the meta-FPGA which worked in a similar fashion. Some guy made a meta-FPGA that sat on top of a Xilinx. You'd load his meta-FPGA, which had all the SRLs connected together in a big JTAG-like chain, and then you could program the meta-FPGA with your own design by loading a serial stream into all the LUTs. Some LUTs were used as LUTs and some for routing. I can't remember exactly why it was useful except that you could write your own open-source router, which apparently was an appealing prospect to somebody.

-Kevin

is very

poor

it self

of

structures.

one

for