timing constraint question (period/timespec)

hey, i'm having some problems with a timing constraint. let's say i have 1 top component that consists of 2 subcomponents. and one of those subcomponents needs a timing constraint like clk period = 100Mhz and the otherone doesn't (if i do it gives me some timing errors). so i thought i'll add the

attribute period : string; attribute period of clk : signal is "100 Mhz";

and i also added

attribute maxdelay: string attribute maxdelay of reset : signal is "10 ns";

in vhdl. but when i do that the compiler (xst) seems to find the maxdelay constraint but not the period constraint? how come? => when i look at the synthesize report it recognizes the constraint but in place and route it doesn't? why does this happen? i really don't have a clue? should i enter the constraint in the UCF? or in the XCF (and how do you make XCF?) ...

thanks for your help,

kind regards, yttrium

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