Hi everybody.
I'm sitting over a partial reconfiguration project for university.
I'm absolutelly new to this topic, but as an introduction to this topic, of course I 've already read the concerning xilinx appsheets and several further sheets from 3rd persons or university papers that are going more into detail.
But they all have something in common. They don't say much about those bus macros, how they work, where to get them or how to create them. They mainly talk about the design flow.
In the last sheet I recently have read that fpga specific bus macros are available over the website of xilinx, but I had no success in finding them there.
Other sheets say, that you have to built them on your own via the fpga editor. But how, when it's absolutelly unclear to me how they work.
I'm also wondering if I have to create one bus macro in the fpga editor per 4 interconnecting signals between dynamic and static parts or if i can reuse one bus macro and instantiate from it several times in my vhdl code.
Maybe someone experienced to this can give me some advises and clarify some things.
The used device is a virtex2pro (xc2vp30-ff896) mounted on the ml310. used software is the ISE and EDK version 7.
Another problem with ISE I encountered is, that after I have build a new system via the base system builder and created a new ISE project from the vhdl-filed created by the EDK, the ISE cannot find those referenced vhdl modules from the xilinx library inside the EDK folder on the hard disk. Instead it marks all the components instantiated with a question mark. Does there exist a possibility to tell the ISE, where to look up for the library modules (a library path or something like that)?
thanks a lot for your help greetings, Lars Schreiber