Has anyone seen any timing specs for the V4 local/regional clocks? I don't see anything in the data sheets. I'm interested in the clock to Q output delay from a local clock pad to an output pad, obviously without using a DCM. I'll probably be using the output SERDES capabilities of the IOB as well.
Thanks!
John Providenza
Howdy John,
Since no one has responded, I'll take a stab.
Tickofcs, mentioned in table 59, seems like what you need - except that the table entry is blank (a little annoying considering that the devices have "been in production" since Feburary).
You should be able to manually add up the various prop delays and come up with a ballpark number. An offset constraint would confirm it. Just to throw around some numbers, I estimate the prop delays through the IBUF, BUFIO, to the OSERDES total about 2.1 ns max... so after you add the clock to out of the OSERDES, you have about 2.7 ns (max) total. If you go through the BUFR as well, add another 0.5 ns or so.
Have fun,
Marc
Marc -
Thanks for the thoughts. I'm hoping a Xilinx person will chime in and explain if there's anything interesting about the local clock input pins near the OSERDES blocks.
John P
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