I am a relatively inexperienced user of Quartus (I did a thesis on it and now I am mucking around trying to get a FM demod working), and I have run into some issues on timing as my design grows large.
I am using a straix part and it is clocked at 80MHz, and I have a number of FIR filters in the design. There are currently 2 FIR filters that need to run at 80MSPS and then a seriec of filters that these feed into after decimation, so these other filters run a lower clock rates.
When I compile etc, the timing analysis gives a stack of critical warnings about the signals between the filters not having enough hold time etc. however it is basing th necessary hold times on the 80MHz clock (I think). I wantd to know how to:1) Tell the timing analysier that these components are running at different clock speeds, and 2) Tell the fitter that 2 filters need to be fit to run at 80MHz and the others dont matter so much, so that I dont end up with the 80MSPS filters being spread out and not meeting the timing requirements whilst the slow ones do.
I hope someone has some clues and that I made sense.