Quicksim/modelsim

I am writing a testbench and one of the clock is a "gated clock" - meaning clock is clocking every time gate goes active. so say that gate pulses at time T. Then clock goes active at T+ 10uS for 200uS. Clock frq. is 25MHz. (clock is inactive after T+210uS) again Gate pulses at T+450uS and clock goes active at T+460uS for 200uS and clock is inactive after T+660uS.

I am not sure how to implement this in Quicksim. can someone give me an example please? I don't want to define high and low for each time. I would think there must be a smart way of implementing this.

I am not even sure how will I write this in Modelsim??

any suggestions?

Thanks in advance

Reply to
martstev
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AAAAAARGH... PLEASE, PLEASE think about the READER when you're writing something that is intended to convey technical information.

You speak of a "gate" signal - is it an input to your system? an output? Why does it pulse - is it some external signal that's outside your control, or are you trying to generate this "gate" pulse? What do you mean by "pulse"? Is it the rising edge of this signal that triggers your 200us of clock activity? Or do you expect the gate pulse to remain true for the duration of the 200us clock stream?

And then what about the clock... is the 25MHz clock an input from an external oscillator, or are you trying to generate it within your design? What do you mean by "clock goes active" - is this the time of the first rising edge you are talking about?

And finally, are you implementing in VHDL? Verilog?

The VHDL code below does something like what I *guess* you want... but I cannot possibly tell from your description. If people insist on technical writing as confused and thoughtless as this, it's little wonder that we engineers have a reputation for being a bunch of incomprehensible geeks with no interaction skills.

--- Model a 25MHz clock generator that runs for 200us after --- each rising edge on signal "gate", with the first rising --- edge of the clock occurring exactly 10us after the rising --- edge on "gate" --- process constant clock_period: time := 40 ns; --- 25 MHz constant start_delay : time := 10 us; constant active_time : time := 200 us; --- How many complete clock pulses will I generate? constant clock_cycles : integer := active_time / clock_period; begin clock

Reply to
Jonathan Bromley

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