If you are making VHDL testbenches you should be writing proper log message s. You should also make your result-checkers properly report mismatches and also allow positive acknowledge. Equally important - your testbench should time out with a good message when waiting too long for an event to happen. And wouldn't it be nice to report a summary of all notes, warnings, errors , etc. at the end of your simulation, or perhaps stop on the fifth error?
All this is supported in a free and open source (and well documented) VHDL testbench Library from Bitvis.
It is my personal opinion that ANYONE making VHDL testbenches should use t his kind of library. It really makes you far more efficient, and it helps e verybody understand both your testbench and the transcript/log from your si mulations. It is extremely easy to use, and you can watch a free webinar or download a powerpoint file for a brief presentation on this library. A quick-referen ce and an example testbench for a simple interrupt controller is also provi ded.
You may load it all down from our website. No registration required.