Updated Stratix II Power Specs & Explanation

Paul,

I am delighted.

Not only is the static Iccint current > 7.568 amperes at 100C, but the device is clearly doing a thermal runaway (in Excel!).

How did you do that? Does the device melt down just like the spreadsheet? It looks as if the solution is iterative, and it keeps trying to converge with the formula for the Iccint being exponetial with T, and the T just getting hotter, and hotter ...)

Sure, when the worst case static current is less than the surge, then there is no "surge...."

Sure. So if the worst case static is 6 ameres, what is the 'surge' at

25C? Less than 6 amperes, but still there?

Smoke and mirrors, mostly smoke?

You should really check your spreadsheets before posting.

EP2S180, Industrial, Maximum, no air flow, no heat sink, no logic (0 power in the blocks), 36 C ambient (runs away, at 35 C ambient it goes to ~85C. Even a 1/2 degree more causes the Tj to pop to 100+.

Now, I admit this is a degenerate case, and people will ususally have some airflow, and maybe even a heatsink. Still ~ 6 amperes just for static current, but at least it won't melt down.

At least V4 won't thermally runaway when you turn it on.

Aust> Hi,

And this post helps the engineering community how?

Well,

John, the issue is "what is the leakage current of the new 90nm technology node?".

Xilinx has claimed (and we think we have proved it) that the use of triple oxide (basically keeping memory cells and pass gates at 130 nm in

90nm) gives us both speed, and a 3X leakage advantage. Not to mention an SEU advantage (we haven't even started on that weakness in the competition, yet).

They claim that their simpler process is more cost effective (? where are the $ quotes ?) and more producable (we are both shipping), and have similar or better leakage, and better speed.

These claims are false. Physics is physics. No smoke and mirrors 6 lut is going to work.

They may have solved the surge issue, but we have yet to see any parts where that is true. It is also true they do not make it easy for Xilinx to buy their parts. We are oblidged to pay for them like any customer, so there is a fair and level playing field. So we admit we may not have seen their fixed parts. Have you?

The engineering community is a group of very well educated professionals who deserve to know what is going on. Most of them have a sense of humor, and appreciate the banter, some do not. If you are one who does not appreciate my postings, please ignore them.

If you objected to the tone of my posting, I am very sorry: I can't help it when I see such total nonsense being presented (IMHO).

If the gentlemanly thing to do is to respond in a "proper" fashion (in your humble opinion), then I will leave that to others, as I am not going to live long enough to tolerate such nonsense. Life is far too precious to me to waste. Perhaps if you knew me better you would understand. Since you do not, please feel free to ignore me.

Again, my intent is to say it like it is, and not to gloss over the fine points, as it is the fine points that leave customers' systems broken and worthless.

Let me know what you are objecting to specifically: the truth of the matter, or the tone I take. I can and do apologize, and I am able to learn, grow, and change.

snipped-for-privacy@xilinx.com

Austin

PS: from the raw message, I can not see exactly where (or who) you are. I respect that, as I too am inundated with spam, and I understand you wishing to avoid that.

John_H wrote:

These posts, between Altera and Xilinx, help the engineering community by exposing and discussing critical design-related concerns.

People (like me) dig around for any potential problems with parts -- especially the brand new ones (which we always need to use).

Although we work very closely with Xilinx on the application of their latest parts, they are not always able and/or willing to disclose *all* of the known issues. Any hint of a potential problem can then be laid out on the table. They are, then, forced to address the issue. Something that may seem benign, to them, may adversely affect our designs.

Having these folks jaw at each other, here, is money in the bank, for us.

Bob

Estimator

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Austin,

You have posted here that the worst-case silicon, 85 C leakage for Vccint only in an LX200 is 3.3 A. Add to that the 416 mW of Vccaux leakage from the xilinx web power calculator (for typical silicon!) and you get a total

*mostly* worst-case silicon, 85 C junction temperature leakage value of 4.38 W. The real worst-case may be higher, since no one from Xilinx has revealed a worst-case Vccaux leakage number.

The worst-case silicon, 85 C junction temperature static power for the Stratix II 2S180 is 5.44 W. That number is plainly visible in our Early Power Estimator at

This means that the Virtex4 leakage is 19.5% lower, with the important caveat that the number is not yet truly worst-case for Virtex4. In any case, hardly 3X. I am amazed that you continue to attack our worst-case silicon power numbers, while Xilinx has not published such numbers for Virtex4. Your customers are going to get themselves into big trouble if they pay attention to your marketing and produce thermal designs for typical leakage, rather than demanding complete power models from Xilinx. If your customers aren't heavily guardbanding their thermal designs, a large part of the silicon you ship them is going to result in operation outside the device thermal specifications.

Of course, leakage is the smaller part of the power story. Dynamic power dominates in most designs, and about 65% of dynamic core power in a typical design comes from the logic and routing. According to your web tool, if I instantitate 72,000 slices (half using their FFs, half not) @ 200 MHz, 25% toggle, the dynamic power with medium routing is 9.05 W.

We find that a Stratix II ALM implements more logic than a slice. However, even if I ignore that, our web calculator predicts a dynamic power for

72,000 ALMs @ 200 MHz, 25% toggle of 8.449 W. If I take into account the fact that an ALM implements, on average, 11% more logic than a slice, I only need 65,000 ALMs, for a total power of 7.63 W. This results is a small total power advantage for Stratix II: 13.1 W vs. 13.4 W. And I did this comparison at worst-case silicon, 85 C junction temperature, where leakage is the most important! Customers running at cooler temperatures will see leakage being less important.

See

for more data, and some real silicon measurements comparing Virtex4 and Stratix II total power on real designs.

Why do we have a dynamic power advantage? Simple: we used a low-k dielectric, as most of the industry has, to increase performance and cut power, while Xilinx did not. Lower k means lower capacitance on all the metal, which is now by far the dominant capacitance. Gives us both a speed and a dynamic power advantage.

The last significant component of power is IO power. Here we also measure that we have an advantage, due to having half the pin capacitance of Virtex4. Also gives us a nice signal integrity advantage.

Add it all up and you find that Stratix II has a power advantage for high speed designs (lots of dynamic power), while Virtex4 has a power advanage for most low-speed designs with low dynamic & IO power. The power differential is never all that large however, so I expect most customers will make their decisions based on performance, price, and features.

Vaughn Betz Altera [v b e t z (at) altera.com]

Hi Austin,

the

The particular case you point out is not thermal runaway. But with no cooling solution at 36 degrees ambient, the junction temperature will be out of spec (the spreadsheet indicates this with 100+). The reality is that anyone using 180,000 Logic Elements and 1000 I/O pins toggling at a couple hundred Mhz will be dissipitating a lot more dynamic power than static, and a cooling solution of some sort will be necessary irrespective of static power.

BTW, we test our chips without heatsinks. They do not go into thermal runway.

with

This iteration is a fundamental based on the physics at work here. Static power is made up of a few components, but at 90 nm sub-threshold leakage is the one that dominates. This occurs because transistors aren't really "off". This is especially true on units that come out at the fast end of the process spread (our Worst-Case numbers... you guys don't seem to publish worst-case numbers), since these transistors are leakier (due to lower threshold voltages, narrower channel lengths, etc.). This sub-threshold leakage power increases exponentially with junction (transistor) temperature.

But junction temperature (Tj) is a function of overall power dissipation and the cooling solution employed. Cooling solutions (package, thermal compound, heat sink, and air flow) can be represented in the end by a "thermal resistance" expressed in degrees/Watt. This thermal resistance times the total power consumed gives the temperature gradient from Ambient (surrounding air) to the Junction. The parameter used to express this resistance is ThetaJA -- the thermal resistance between junction and ambient.

So we have: Power = DynamicPower + StaticPower(Tj) Tj = Ta (ambient) + Power * ThetaJA

As you can see, solving for the junction temperature requires iteration. Let's say you've got a chip that burns 1 W of static power @ 25C, and is generating 3W of dynamic power (temperature insensitive). This is a total of 4W at 25C. With no cooling solution, let's say there is a thermal resistance of 10 degrees per Watt between the junction (transistors) and ambient (surrounding air). Let's say the ambient temperature is 25C.

Iteration 1: Tj = 25C (ambient) --> Static Power is 1W Iteration 2: Tj = 25C + 4W * 10 deg/Watt = 65C --> Static Power is now (say) 2W Iteration 3: Tj = 25C + 5W * 10 deg/Watt = 75C --> Static Power is now (say) 2.3W Iteration 4: Tj = 25C + 5.3W * 10 deg/Watt = 78C --> Static Power is now 2.4W Iteration 5: Tj = 25C + 5.4W * 10 deg/Watt = 79C --> ...

As you can see, we converge on a Tj of ~80C in this hypothetical example.

Thermal runaway occurs when the this iteration reaches a point where the incremental amount of static power for a 1 degree change in temperature is greater than the cooling solution's ability to dissipate that power. For example, with a 10 degrees per Watt ThetaJA solution, if we were to ever reach a junction temperature where the Static Power increased by more than .1 W/deg, then the static power would increase faster than we could dissipate and this iteration would result in an infinite junction temperature. In practice, the chip would release the magic smoke that keeps it working.

at

At any temperature, worst-case or typical or best-case silicon, there is no surge current. A power supply designed to meet operating conditions will result in succesful device power-up.

- Paul

Paul, nice tutorial. You are a good teacher!

But let's look at the so-called reduction of 47% in the Altera leakage current specs: Here is the change in worst-case 85 degree static power (the only static parameter that really matters) from the previous 2.0 to the new 2.1:

2S15 increased (!) by 48 % 2S30 reduced by 1 % 2S60 increased by 4 % 2S90 unchanged 2S130 decreased by 6 % 2S180 decreased by 14 %

It takes creative marketing to call that a 47% reduction in leakage current !

Peter Alfke

Paul,

OK. So they do not runaway (in silicon). Should really fix the spreadsheet so it doesn't look like it does.

In a similar situation, our web based tool does not "blow up." It will report the actual junction temperature (say 108 C) which will let the designer know that they have exceeded the temp, and also give them an idea by how much they have exceeded the temp.

A matter of personal preference perhaps?

By stopping all data reporting beyond 100C, you hide the leakage current vs. temperature curve (beyond this point), which makes it harder to see just how bad it can get.

At least we show the whole curve.

And, as for the surge, the statement you made below is the best description (perhaps the only description) of 'no surge': if the tool says I need X amperes for the design, and I supply X amperes, the design will power on, configure, and work. (Since that is what you clearly said below.)

Sincere congratulations on fixing the surge.

Our customers have been very happy that we did that six years ago for Virtex II (and kept it out of subsequent product).

Austin

Paul Leventis wrote:

leakage

It was an "up to" number. You should be familiar with these ;-). The biggest change was in the typical specs.

Speaking of which, where are the V-4 worst-case static power numbers? They are the only numbers that matter, but somehow you still haven't published any for V4...

Old data was pre-silicon data for many family members. Icc was based on projections. Turns out the curve is flatter than expected, so smaller devices have more current than expected and larger devices have much less current. This is even more evident in the new typical numbers:

25C 85C 2S15 +63% +10% 2S30 -14% -24% 2S60 -17% -19% 2S90 -31% -28% 2S130 -38% -34% 2S180 -38% -38%

Now, I think I did my math wrong somewhere in here because I know there is one that decreased by 47%. But you get the idea.

Righteous indignation from Xilinx for use of an "up to" number? Give me a break.

Paul Leventis Altera Corp.

Austin,

You railed against Altera and your comments on the tool and their parts were obscured by the sheer volume of sarcasm. Maybe if I knew you, I'd take extreme sarcasm as appropriate critique; I just wasn't brought up that way.

There are those who believe triple oxide is the way to go. There are those who believe low-K dielectric is golden. There are others in the industry stepping away from low-K because they see a path to 65 nm and beyond without the need for the exotic materials. As with politics and religions, there are data to back up the claims by both camps, not just "I'm right, you're stupid."

I find it difficult to ignore "attacks" from any vendor. I've been primarily using Xilinx devices over the last decade having first cut my teeth on the Altera devices. I prefer brand X because of problems I had getting appropriate I/O performance on brand A as little as 5 years ago. For me, brand X was a superior technical solution for my needs. I don't like to see anyone "disrespecting my parts" out of spite nor do I like to see someone in "my camp" producing a virtually useless discourse on how much the competition lies and cheats.

If someone believes in their product - or religion, or politics - I don't mind listening to their discourse when it's not offensive. When their message degrades to mud slinging and name calling - as it appeared to be when an Altera marketing VP posted here several months ago - it brings the whole forum down a notch or two.

It appears Altera's power estimators have some bugs. It appears Xilinx hasn't published worst-case numbers on all power figures. It appears Triple Oxide is a win for Xilinx. It appears Low-K is a win for Altera. It appears that most marketing messages are more politics and religion than fact. It appears Engineers on both sides of the camp believe their marketing. That's fine.

It appears I get annoyed when people turn argumentative for the sake of argument.

I've been a hardware engineer at Xerox Corp since '99 - john dot handwork at office dot xerox dot com - and use my home email to limit spam. There's typically no reason for my work email on this forum. I made Telecomm test equipment at TTC (Telecommunications Techniques Corp, now Acterna) in Germantown, Maryland for a dozen years before switching to color laser printers here in Wilsonville, Oregon. FPGAs are my daily work.

Thanks for your continued contribution of useful information. I appreciate all the folks on this board that help expand my horizons with respect to FPGA design. I don't want to be sorry about respecting my field.

- John Handwork

John,

Thanks for your posting.

A very few comments below.

Aust> Austin,

OK, fair enough. I have been told that my 'style' is a mystery to some. I am working on it.

We see some benefits: low leakage for memory and interconnect, higher speed for interconnect, better SEU FIT rate (lower) for memory....

There are those

We'd love to have lo-K! But our fabs (yes, plural) could not meet our reliability goals for qual. So we ended up pushing the Vt's to get back the speed we lost, and paid for it with slightly increased leakage in V2 Pro. In V4, we don't need lo-K to get the speed we needed.

There are others in the industry

As it turns out, we can now have lo-K, and have it committed for 65nm. They finally got it working to our requirements.

As with politics and religions, there

Well, I would NOT say they are stupid, as they have explained why they made their choice: triple oxide was considered too much of a risk at their fab at the time they did their design. For us, lo-K was considered too risky. You do not get to choose, the fab chooses for you.

Thank you.

I prefer brand X because of problems I had

I hope we can continue to show that our offering meets your needs. I am sure that Altera can also make a decent showing to meeting your needs, as well.

In no way are their parts "bad" or "slow" -- they are a serious competitor with a competitive offering (to our Spartan, Virtex 4 LX and SX families, although I would state that we have no competition to the FX family .... yet).

I don't

Paul does not lie. He does not cheat. I did not say that. If you read our postings carefully, you will note that he, and I, are very very careful about what we post.

When they ran their benchmarks, they saw a speed improvement. When we run our benchmarks, we see a speed improvement. When I run our power predictor spreadsheet, I see an improvement. When Paul runs his, he sees an improvement.

The devil is in the details: is a static power reduction at 25C an improvement? Yes, and No. Is comparing our middle speed grade with their fastest honest? Well, if that is the only thing they can get their hands on, perhaps it is. Would it be better to compare their slowest with our slowest? Who would be excited about that?

True. We have not finished all characterization. Our FAEs have the present worst case numbers for customer design, but we prefer to let them cool a little longer. Use Web power to 85 C junction temp and multiply by 2.5 to get worst case (for now, until we release the finals). Even then, we are still up to 70% less leakage.

Yes. 70% better worst case leakage is big. SEU improvement is good. Speed is good.

5% less C, means 5% less core power, and ~5% more speed over regular K. All good.

Sadly, true.

Yup. But I get to tell marketing what numbers to use, before they use them. I don't know if Paul is also the manager of their characterization group.

Cool. I bought and used TTC test equipment in my 23 years as a telecommunications transmissions system designer before I was reincarnated as an IC Design Engineer. Great equipment!

You are welcome.

I don't want (you) to be sorry about respecting my field.

Austin Lesea wrote: (big snip)

I wonder what fraction of FPGA designs are not very speed sensitive. I used to wonder about that in TTL days, building digital clocks (60Hz for the fastest signals) out of 30MHz TTL chips.

Many designs could easily only require on half or one tenth of what current FPGAs are capable of, and still be worth putting in an FPGA. For those, the slowest devices, especially with lower static power, might be very useful.

For the most part, I don't find this discussion very useful. We all know about marketing departments, and having engineers argue this doesn't cause me to look favorable on their company or products.

-- glen

with

they

you.

No, the main reason we chose not to use triple oxide was we found that it hurts speed too much for the resulting reduction in static power. There are other levers to use (varying gate length, threshold voltage) that also reduce static power and can do so with less speed hit. Obviously, your engineers came to a different conclusion.

My guess is the real reason for the difference in approach comes down to different product goals and performance/power targets. In the end, we chose a different point on the speed vs. static power curve for Stratix II than you did for V4. You can talk about "system performance" until you are blue in the face, but in the end our logic + routing fabric is significantly faster than V4s. That's where the bulk of the transistors are still, and we chose faster, leakier transistors where you chose slow, less leaky ones.

Regards,

Paul Leventis Altera Corp.

Could you post some details on how you are getting this "up to" 70% leakage number?

If I take 85C Typical data from WPT4.0 for V4 and multply by 2.5 (VccInt + VccAux), and compare to 85C Maximum data from the PowerPlay Early Power Estimator 2.1 for Stratix II (VccInt + VccPD), here is what I find.

LX15 580 mW 2S15 825 mW -29% LX25 840 mW LX40 1212 mW 2S30 1191 mW +2% LX60 1782 mW 2S60 2232 mW -20% LX80 2210 mW LX100 2817 mW 2S90 3233 mW -13% LX160 3727 mW 2S130 4411 mW -15% LX200 4542 mW 2S180 5445 mW -17%

I have a graph that plots vs. normalized LE count since device sizes don't line up perfectly, but you get the picture.

Now I know the 2.5x factor is a rough estimate on your part, but I still find it hard to see a massive V4 advantage on static power here. And if we add in our dynamic power advantage (see Vaughn's posting)...

Regards,

Paul Leventis Altera Corp.

Paul,

OK. There it is folks: they are leakier. Seems their fab did not show any improvements they felt were worth having.

And, if you decide to use only LUTs and interconnect, and not take advantage of any advanced features (SRL, LUT RAM, FIFO/BRAM, BRAM w/ECC, PPC, EMAC, DSP48, and so on and so forth), nor attempt to push our tools, you can also get faster performance, too. (Although I am still very suspicious of this claim).

But, if you are serious about static power, and concerned about getting the best performance, and willing to actually use some of the hardened (faster) functions, then I ask you to consider the Virtex 4 FPGA.

And if you need built in source synchronous IO with individual pin settable or adjustable delays, 450 MHz PPC, EMACs, or MGTs, well, there is no other choice, is there?

Aust>>Well, I would NOT say they are stupid, as they have explained why

Paul,

Sign up, and watch Peter.

Aust>>True. We have not finished all characterization. Our FAEs have the

I did. My question remains unanswered.

- Paul

Thanks to John for a thoughtful posting. I enjoy reading this newsgroup and helping customers when I can. I also can't resist correcting errors / misrepresentations when I see them. I don't think name calling or hyperbole is enjoyable for either the people posting or the people reading posts, so I appreciate the effort to encourage civility.

Hopefully correcting the error below will not cause a firestorm in response:

FSG dielectric (Virtex4) has a dielectric constant of 3.7. Black diamond (Stratix II) has a dielectric constant of about 3.0. See

for details on the dielectric constant of black diamond. That means you get a 19% capacitance reduction with black diamond vs. FSG. Everybody remembers capacitance is directly proportional to dielectric constant, right? :).

So all metal capacitance drops by 19%. Nowadays metal capacitance is about

2/3 of the switching capacitance in an FPGA, while the remaining 1/3 is gate & diffusion capacitance that is unaffected by low-k (since it's transistor capacitance rather than in the metal stack). So, you get an ~13% speed up and ~13% dynamic power reduction from the use of a low-k dielectric.

Vaughn Betz Altera [v b e t z (at) altera.com]