Strange clock problem with Synthesized netlist in Quartus

Hi Folks,

I have a strange problem with the synthesized netlist. I use the Verilog module below to generate a clock. At RTL level, it works fine. When I tried simulating the synthesized netlist, I noticed that both the rising edge & the falling edge of the clock output "outclk" are red. I am using Quartus v4.2 & ncsim for the simulations.

Thanks for your help Arun

module CLKDIV ( inclk, // Input data clock divby, // Divisor outclk, // Output Clock reset_l);

output outclk; input [07:00] divby;

input inclk; input reset_l;

// begin reg [07:00] rCount; wire isEqual = (rCount == divby);

always @(posedge inclk or negedge reset_l) begin if (!reset_l) begin rCount

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