Synthesis Problem

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First, the indenting is very confusing.

So, asynchronous reset, since it is in the sensitivity list.

But it is dependent on enable? I believe you can have either asynchronous or synchronous reset, but not some of each.

Try to make a very simple counter, with either asynchronous or synchronous reset, and a count enable. It has to match what the real FF's in the real FPGAs do.

this should be a 4 bit down counter with asyncronous reset(0 active),with an enable that plays the role of a 'start' for the counter(that's why I chose to change the value of "a" depending on enable because enable isn't always "1"->in my project enable= out_of_a_clock_devider & out of a DFF which has as inputs "start" and "stop")

I just can't make this counter work..in modelsim everything is fine... If anyone knows how to fix it..please help me...

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I forgot to say that when I reset it, the counter has to take the preset value and start countering from that value - that's why I have a preset there.

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I think part of the problem related to enable.

It is hard to follow the logic through a, and maybe the tools also can't figure that out, but you don't want enable to apply to the reset, otherwise it isn't an asynch reset. I think that is part of the problem. You might also need enable in the sensitivity list, otherwise, and being inside the always block, the assignment to a is also a register. Actually, remove a. Just do all the assignments based on clock, reset, and enable, and be sure that reset applies independent of clock and enable.

-- glen

Does your target device allow presetting to a variable (non-constant) value? (probably not).

Follow the templates in the user guide, at least until you get a better idea of what works and what does not.

Your enable and reset logic is messed up. Think about priorities of inputs. (e.g. highest priority is reset, second is (clocked) enable, etc.) Code accordingly (e.g. if-else). For example, you reset, but then you run other code that affects those same outputs, negating the effect of reset.

When you say it is fine in modelsim, did you actually simulate it (thoroughly) and the results are good, or did you just compile it? This is not a language issue (modelsim compiles it), it is an issue where you are not properly describing the behavior of hardware that can be constructed in your target FPGA.

Andy

In modelsim it worked with testbench and all..the results were good

I re-wrote the code like this but it still gives me those errors :(

module counter9 ( clock , reset , enable , counter_out, carry_out, preset ); input clock ; input reset ; input enable ; input [3:0] preset; output [3:0] counter_out ; output carry_out; wire clock ; wire reset ; wire enable ; wire [3:0] preset; reg [3:0] counter_out ; reg carry_out;

always @ (posedge clock or negedge reset or posedge enable) begin : COUNTER if (reset == 1'b0) begin counter_out

So how does assigning 'enable' to 'a' synchronously make enable work like 'start'? If enable is a pulse that should make the counter run forever then I don't think you have the right logic for that.

As for the little synthesis problem(s), you describe a counter that can both decrement the counter and increment by 9, at the same time. Fairly exotic hardware, that. Similar thing with a. Hence the error message from XST.

This is why logic is usually described so that you have one top level if in an always block. One branch for reset, the other for the interesting stuff. Within the same level in an if structure you can contradict your assignments to your heart's content and the last one will be in force at the end of the clock cycle. Just be sure that's what you wanted.