problem with synthesis

The following module generates this error: The logic for does not match a known FF or Latch template. The logic for does not match a known FF or Latch template.

What I want to do is to have a module that can keep the input signal d high in 'ld' for a certain amount of time (16 clocks). During that time period, led would blink with a frequency clk_freq/(2^blink_freq).

THere are a couple of problems

1) I need a module register to hold the signal 'd' when it goes high, usually 'd' only maintains high for a single clock period.

2) I need a test when 'd' is no longer active and after a certain amount of time, led should turn off. Now my code has a precision problem, it does not reliably count high time.

I need help to straighten out this code. Where can I get some sample verilog to look at (small modules that implement simple things)?


module blink(input clk, input d, output reg led); parameter blink_freq = 23; paremeter high_time = 4; // 16 clocks reg ld = 0; reg [blink_freq:0] count; reg [high_time:0] hcount;

always @(posedge clk or posedge d) begin if(clk) begin count

Reply to
Fei Liu
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simulate this first

initial count = 0; initial hcount = 0; initial ld = 0; initial led = 0;

always @(posedge clk) begin count

Reply to
Muzaffer Kal

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