How do I constraint multiple clock cycle in Altera?

Hello everybody,

My Altera design uses multiple clock cycle and negative clock edge, how do I constraint it? Here is my code, absolute_addr is generated 1.5 clocks earlier before consumption.

I am reading the Quartus II Classic timing analyzer manual, but am not clear how to constrain this logic.

Hope you can help me out.

Many thanks from newsreader.

// My code segment

reg start_sequence; reg [2:0] addr_en; // one-hot reg [31:0] absolute_addr; reg [1:0] ram_ba; reg [15:0] ram_row; reg [7:0] ram_col;

always @(posedge clk_100m or negedge arst_n) begin if (!arst_n) begin addr_en