Verilog Program With A Problem

Hi to all,

I'm writing a program using verilog at the moment. The program that i'm doing now is one of many blocks that will be finally linked up together...Right now, i'm having some problems with my program...In my program, i have a part where i need to compare the input(eingated) & an output(eout_prev) of another program which is a D flip flop. So in my program what should i define "eout_prev" as? An input, output, reg ...? I need help urgently. Anyone can help me out ?

Thanks a lot! :-)

Below is my program & the D flip flop program ,and i have pointed to where my problem lies.


`timescale 1ns/1ps

module encoder(eingated, clr, clk, keydet, inhibit, eout); input [3:0]eingated; input clr, clk; output keydet, inhibit; output [3:0]eout; reg [3:0]eout; reg keydet, inhibit;

parameter idle = 1'b0, keypressed = 1'b1; reg [1:0] cur_state, next_state; reg eout_prev;

always @(posedge clk or negedge clr) begin if(clr==0) cur_state = idle; else cur_state = next_state; end

always@(cur_state or eingated or eout or eout_prev) begin case(cur_state) idle : if (eingated == 4'b1110 || eingated == 4'b1101 || eingated == 4'b1011 || eingated == 4'b0111) begin keydet = 1'b1; inhibit = 1'b1; next_state = keypressed; end else begin keydet = 1'b0; inhibit = 1'b0; next_state = idle; end

keypressed : if (eingated == 4'b1110 || eingated == 4'b1101 || eingated == 4'b1011 || eingated == 4'b0111) if (eout == eout_prev)

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In module encoder, "eout_prev" is an input

"Bose" ?ÈëÏû?ÐÂÎÅ :



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Peng Cong

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