Using the 7 segment displays on Xilinx Spartan 3 kit

I am trying to understand the working of the multiplexed seven seg. displays on the xilinx spartan 3 board.the manual does not give me detailed info. I am trying to write a simple program where I switch a switch to the on position and it should display "0012" on the displays. Any suggestions please?

thanks

Reply to
fpgawizz
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Hi.

Here's some code that I used to display digits/letters on the 7-seg displays:

module set_7seg_displays ( // *** Inputs *** input wire clk_50mhz, // System clock. (50 MHz) input wire btn, // Button 0. (Active High).

// *** Outputs *** output reg [3:0] digit,// 7-seg display enables. (Active Low). output reg [7:0] seg // 7-Segment display. (Active Low).

);

// 7-Segment display. seg[7:0]={ca, cb, cc, cd, ce, cf, cg, dp}. wire rst_n; // System Reset. (Active Low). reg [25:0] slow_cnt_h; reg slow_clk_2h; reg slow_clk_h; reg [1:0] cd;

// Assign reset to a button push. assign rst_n = ~btn;

// *** Create a 2x 7-Seg display clock *** always @(posedge clk_50mhz or negedge rst_n) begin : CLK_GEN_2x_7SEG if (!rst_n) begin slow_clk_2h

Reply to
jeremy.webb

Hi Jeremy,

since this _is_ tutorial stuff, I must point out that clocking from derived logic is a very very bad idea. I'm sure you must have ignored tools warnings to get this to compile.

FPGAs have dedicated paths for the clocking lines separate from logic .. and the twine shall never meet. There are so many reasons why this is a bad idea, but basically the tools have to contrain timing quite intensely to get this working at all and you might just have been lucky.

The correct way to derive a new clock is using a DLL, DCM, PLL, what have you. In this simple case however, there's another simple fix you could use: Just calculate which cycle of the fast clock is safe to use.

... wire [26:0] slow_cnt; wire slow_ce = slow_cnt == 2*'h001_86A0; always @(posedge clk_50MHz) begin slow_cnt

Reply to
Tommy Thorn

I think everyone who gets the starter kit must end up writing their own driver for the 7 segment display.

Shame there isn't a bit more simple 'IP' provided with the kit.

Apart from the Xilinx examples I didn't find much in the way of resources for the starter kit on the web.

Would there be interest in a Yahoo group or something to share Spartan 3 starter kit related files?

Reply to
nospam

Grief, pre-coffee post. Should know better. Slight better code:

reg [26:0] slow_cnt; always @(posedge clk_50MHz) if (slow_cnt) slow_cnt

Reply to
Tommy Thorn

Yes. I would be interested in a usergroup for xilinx spartan 3 kit users.

Reply to
fpgawizz

Hi,

Please check out

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for a set of labs/experiments you can try with the Spartan-3 Starter kit... I have tried to touch on most of the resources with the exception of the SRAM.

// opinion_on

This kit is well named, a "starter" kit. If everything is simply handed to you, you don't learn anything. That's why it makes such a great educational tool.

If a time multiplexed seven-segment display is challenging enough for someone to make an appeal to this newsgroup, they should go through the exercise of designing it themselves. Maybe with a little help... We are all learners, just at different places on the path. I think to include resources like this with the kit itself (or posted to this newsgroup) defeats its utility as a learning tool.

// opinion_off

Good luck! Eric

Reply to
Eric Crabill

Hi Tommy,

As far as synthesis or p & r warnings for the code I provided above, I can't recall seeing any. This wasn't a timing critical design, and the code was mainly used to get a quick and dirty measurement of the required clock speed to keep the 7-segment displays lit while multiplexing between the 4 displays. And it was also used to test the multiplexing scheme for the displays.

Thanks for the info,

Jeremy

Reply to
jeremy.webb

Thanks for the pointer.

I didn't buy the kit to learn FPGA basics, I bought it as a cheap development platform.

I spent about 3 hours pawing through the documentation to write a top level verilog module and matching constraints file which defined all the I/O on the board and expansion connectors. I didn't learn anything it was just tedious and error prone. The only thing I discovered (learnt) writing a hex display module for the 7 segment LEDs was that the anodes have inverting drivers.

I wrote the hex display module to use as a diagnostic tool.

That is the kind of basic 'IP' which I was disappointed not to find in the box.

But would enhance its utility as a development platform.

Reply to
nospam

The example 'Digital Clock using Multiplexed 7-Segment Display' has VHDL code on how to do the multiplexed seven segment display.

The example can be downloaded from:

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Cheers, Shalin-

fpgawizz wrote:

Reply to
Shalin Sheth

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