Hi all, i have a verilog design in which some of the modules are similar to the one given below. it has to shift right the input by 4 for first 10 clock cycles and shift right by 5 from the next clock cycle. it works fine in the simulator.
but when i actually tested it in hardware(fpga), tmp register does not increase at the rising clock cycle. it keeps increasing, so the output is always shown right shifted by 5. how do i make it work. do i have to send the tmp out and read it in the next clock cycle. is there any other way to do it, because there are many counters used in the design.
module app(ain,aout,clk,reset); input [31:0] ain; input clk,reset;
output [31:0] aout; reg [31:0] aout; reg [31:0] tmp; // here i am using tmp just as a counter.
always @ (posedge clk or negedge reset) begin if (!reset) begin aout=0; tmp=0; end else begin if(tmp>4; tmp=tmp+1; end else begin aout=ain>>5; tmp=tmp+1; end
end end endmodule
thanks a lot, sr