This may sound trivial but why is data being output (read) on the out port during the write cycle in the Xilinx inferred RAM examples such as:
if (CLK'event and CLK = '1') then if (en = '1') then if (we = '1') then ram(conv_integer(unsigned(addr)))
Reading RAM while
Oct 12, 2004
3 Replies
because if there is a writing access (we = '1') then the input data (di) is registered both in the corresponding memory location and in the output port (do), according to the following lines:
if (we = '1') then ram(conv_integer(unsigned(addr))) as:
Why do you think this should not be done? Don't you expect something to appear on the do output? What would you expect the do output to have?
Rick "rickman" Collins
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