Simple Memory Read problem, help appreciated

Stupid me, I should have an asynchronous read....

Now it looks like this:

PROC_ram : process (clk) begin if (clk'event and clk = '1') then -- memory write: if (ew_cp0 = '1') then ram(conv_integer(unsigned(rw_addr_cp0)))

Well .. unfortuatnely XST tells me that the RAM will be implemented with LUTS and that I have to describe it in a way that BRAM can be instatiated, so that initial values can be stored in it...

Anyone who can help me out in this matter?

Xilinx has templates for how to write code that will infer memory that can be implemented in ram blocks. Check the documentation.

I'm guessing that the problem area might have to do with your reset section. Try taking out the entire 'if (rst = '0')....end if;' section of code and see if it infers the memory correctly.

Kevin Jennings

Thanks Kevin, but the problem remains... Without the reset, the tool still tells me that when i have an asynchronous read and so BRAM cant be used... I am using XST 7.3. Anyone a workaround for this problem?

Would be very much appreciated

Seems pretty clear to me...use a synchronous read

Once again, we call on that Spanish hero Manual

Per Xilinx's website

Templates for inferring registers, flip-flops, or memory can be found in Chapter 2 of the XST User Guide at:

Although a more useful link is

Page 174...

Kevin Jennings

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Alright, thanks for the feedback peter. The problem is, that I need an asynchronous read for the module I am using. So the problem is, that I cant initialise the values in the RAM as in the BRAM.

Is there any other way to get initial values into the asynchronous RAM? Does an upgrade to a newer version of XST help or am I doomed?

Thanks G

Take a look at /Xilinx/doc/usenglish/docs/lib/lib.pdf. Look up component RAM_16x1D. There are examples on setting the initial values of RAM.

More importantly, be familiar with the various documents under the /docs/ subtree. The developers reference and constraint guide are equally invaluable.

THanks John, will have then a look at it. Just hope that it also works with my old XST 7.1...

In which case you have to have the single clock latency that you described - sorry - that's just the way BRAMs work.

Cheers, Martin

Yes, I am now using the Core generator to generate a distributed RAM with latency zero. Will be a little bit more painful, but hope to get it working with initialising it. Obviously the sythesis will take a lot of time and occupy a lot of logic but this I will accept now for a test!

Maybe I have to rethink and rewrite the design to be conform with sychronous BRAM!