Instantiate RAM in Spartan3

Mar 31, 2005 3 Replies

Hi, I need to instantiate a RAM in my Spartan3 FPGA. I need to be able to address 256 spaces, each space 8 bits, and maybe 5k samples..... I am trying to set this up for DNL and INL testing. Any idea on how to set this up??? I have looked at memory symbol in Xilinx, but none seems to satisfy this condition. So basically, I have data from 0 to 256 coming in, and I need to count how many times a data hit....Like for example, if I have 0, 1, 1, 2, 3, 3, 3 4, 5, 6,



255, 256...my count for bin 0 would be 1, for bin 1 would be 2 for bin 3 would be 3, for bin 255 would be 1, etc.. Thanks, Ann

address 256 spaces, each space 8 bits, and maybe 5k samples..... I am trying to set this up for DNL and INL testing. Any idea on how to set this up??? I have looked at memory symbol in Xilinx, but none seems to satisfy this condition. So basically, I have data from 0 to 256 coming in, and I need to count how many times a data hit....Like for example, if I have 0, 1, 1, 2, 3, 3, 3 4, 5, 6,

255, 256...my count for bin 0 would be 1, for bin 1 would be 2 for bin 3 would be 3, for bin 255 would be 1, etc.. Thanks, Ann

That's a "histogram memory".

Use an ordinary 256 x 8 ram. When you get a hunk of 8-bit data "D", set the memory *address to D*; read the ram, increment that, and write back. Stopping the incrementer at 255 is a good idea. You'll need a little state machine to manage it.

John

You'll need a

If he use a dual port data ram he will not need a state machine

1 port for reading the data to increment and the other to write the new value

---------------------------- adress_read

Hi, I tried to do what you said about using the data as the address for the RAM, then increase Data_out and then write back, but this for some reason doesn't work right. I can see that if my write signal changes from 0 to 1 from state read to state write on every clk edge, there is no data in the RAM. If I just let the write signal remains constant, then there will be data in the RAM. But this wouldn't be a histogram, it's just raw data. Has anyone successfully doing this? I don't want to use the dual port RAM because if you read from port A and write to port B, then the next time when you read again, your data from A hasn't changed, so basically you are not really doing anything to your memory content in the end, except increase by 1. Thanks, AL

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