Synplify is not translating xilinx template for block ram

The xilinx template for V4 block ram with one read/write and one read port is not synthesizing correctly in the synplify. The original code maps into LUT rams. If we latch the input address and include a synthesize directive for block RAM then it creates two block RAM instead of 1 one for each read port. Why it is like that. Is there any way we can corrct this behaviour. Else how can we integrate a synthesized output from xilinx to synplify. That is i want to synthesize the module contaiig this RAM in xst correctly and then combine that synthesized output to synplify and then resynthesize it. Is this type of design flow possible. regards Sumesh V S

Reply to
vssumesh
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I've been able to infer dual port block rams in synplify with no problems before. Can you post a test case that fails? Help us help you.

Andy

Reply to
Andy

I would start with the synplify template.

-- Mike Treseler

Reply to
Mike Treseler

The code which i used from the xilinx template is always @(posedge clk) begin if(we) RAM[addr1]

Reply to
vssumesh

It may seem the same, but try

// (using your own dimensions) wire [n:0] RAM_addr1 /* synthesis syn_keep = 1*/ = RAM[addr1]; wire [n:0] RAM_addr2 /* synthesis syn_keep = 1*/ = RAM[addr2]; always @(posedge clk) begin if(we) RAM[addr1]

Reply to
John_H

Hello John, This is also not working. It is creating distributed RAMs. Is there any problem with the version of synplify. I am using 8.0. Also used syn_ramstyle directive.

One more thing not related to this issue; can you guide me to some good study materials about synplify synthesize techniques and constrains (different clock domains, clock relations etc etc). And xilinx PAR techniques.

Reply to
vssumesh

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