The xilinx template for V4 block ram with one read/write and one read port is not synthesizing correctly in the synplify. The original code maps into LUT rams. If we latch the input address and include a synthesize directive for block RAM then it creates two block RAM instead of 1 one for each read port. Why it is like that. Is there any way we can corrct this behaviour. Else how can we integrate a synthesized output from xilinx to synplify. That is i want to synthesize the module contaiig this RAM in xst correctly and then combine that synthesized output to synplify and then resynthesize it. Is this type of design flow possible. regards Sumesh V S
- posted
17 years ago